One of the most important RF building blocks today is the frequency synthesizer, or more particularly the programmable frequency divider. A frequency synthesizer is an electronic system for generating any range of frequencies from a single fixed time base or oscillator. They are found in a wide variety of electronic systems across multiple applications from high volume low cost consumer devices to low volume high performance military systems. Frequency synthesizers may be found for example within radio receivers, mobile telephones, cellular based smartphones, wireless gaming consoles, satellite receivers, and Global Positioning Systems (GPS). Typically, three types of synthesizer are commonly distinguished of which the first and second types are routinely found as stand-alone architectures, these being Direct Analog Synthesis (DAS), also called a mix-filter-divide architecture, and Direct Digital Synthesizer (DDS). The third type and the most commonly found in communication system integrated circuit (IC) building-blocks are indirect digital phase-locked loop (PLL) synthesizers which are based upon integer-N and fractional-N techniques.
A PLL is a feedback control system which compares the phases of two input signals and produces an error signal that is proportional to the difference between their phases. This error signal is low pass filtered and used to drive a voltage-controlled oscillator (VCO) which creates an output frequency. The output frequency is fed through a frequency divider back to the input of the system, thereby producing a negative feedback loop. If the output frequency drifts, the phase error signal will increase, driving the frequency in the opposite direction so as to reduce the error. Thus the output is locked to the frequency at the other input which is usually derived from a crystal oscillator and therefore a source very stable in frequency. Accordingly, frequency dividers may be deployed both to reduce the crystal oscillator frequency for use as the reference and within the feedback loop.
In either instance the ability of a frequency synthesizer to generate multiple frequencies, and thereby provide RF circuits with the ability to transmit/receive on multiple frequencies is the programmable frequency divider. This is usually in the form of a digital counter, with the output signal acting as a clock signal wherein the counter is preset to some initial count value, and counts down at each cycle of the clock signal. When it reaches zero, the counter output changes state and the count value is reloaded. Such circuits are straightforward to implement using flip-flops which are digital in nature and easy to interface to other digital components or a microprocessor. This allows the frequency output of a synthesizer to be easily controlled by a digital system.
However, the frequency divider consists of logic gates that operate at, or close to, the highest RF frequency as it is driven by the oscillator which has the highest speed in the RF circuit. Accordingly, the divider's complexity and high operating frequency, normally leads to high power dissipation wherein optimizations are typically beneficial and difficult to attain. However, one of the most crucial aspects of the present-day consumer electronics industry is the short time available for the development of new products to potentially their global dominance of a market. These short time-to-market product demands require IC designers to employ architectures that provide easy optimization for power dissipation, fast design times and simple layout integration, see for example Vaucher et al “A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35 μm CMOS Technology” (IEEE J. Solid-State Circuits, Vol. 35(7), pp 1039-1045, hereinafter Vaucher1).
High reusability, in turn, requires an architecture that provides easy adaptation of the input frequency range and of the maximum and minimum division ratios of existing designs to the new application requirements. Accordingly, the selection of the divider architecture is therefore important for achieving these desirable characteristics of low-power dissipation, high design flexibility and high reusability of existing building blocks. Within the prior art probably the most popular and widely exploited architecture is the Dual-Modulus Prescaler (DMP) based architecture which overcomes the problem of generating narrowly-spaced frequencies that are nevertheless too high to be passed directly through the feedback loop of the system wherein there are two separate frequency divisors employable, usually M and M+1. Whilst the DMP is easily implemented it cannot generally synthesize all the required frequencies and its programmability is further limited if a delta-sigma (ΔΣ) noise shaper is designed within the fractional-N synthesizer, where the instantaneous division ratio varies around the average correct division ratio. Therefore, a Multi-Modulus Divider (MMD) architecture which extends the DMP is desirable within the ΔΣ fractional-N frequency synthesis. An alternative prior approach is the Pulse Swallow Divider (PSD) wherein a prescaler, for example a DMP initially divides the input frequency, Fin, by N+1 or N based on a modulus control, wherein the prescaler output is divided by both a swallow counter which divides the prescaler output by a programmable factor S in feeding back to the prescaler and by a program counter at a fixed rate P to generate the output frequency, Fout. Accordingly, Fout=(Fin/(NP+S)).
However, these dividers whilst offering benefits over DMP also have disadvantages which vary according application. For example, in many applications the frequency divided signal should have a duty cycle of approximately fifty percent so that it emulates a clock signal at the divided frequency whilst in other applications the divided frequency should have low jitter with respect to the high frequency input signal Fin or be capable to supporting unlimited range with either non-continuous or, preferably, continuous division. Within the prior art focus has been placed to the earlier issues such as clock frequency, accumulated clock jitter, and non-continuous division ratio setting rather than extending range and providing pseudo-continuous or continuous division.
Accordingly, the inventors present initially a modified MMD which provides extended division range against the prior art and provides pseudo-continuous division and show that this still yields an incorrect division when the division ratio is switched back and forth across the boundary between more than two different ranges. The inventors also present an extension of these concepts that remove this issue and provides for a continuous division over more than two extended ranges. Accordingly, embodiments of the invention presented by the inventors solve the whole continuous division extended range problem and provide for MMD frequency dividers with no drawbacks.
Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.